1. Field of the Invention
The present invention relates to dynamic random access memory (DRAM) semiconductor devices and systems, and more particularly to methods and apparatus for generating an internal array voltage.
2. Description of the Related Art
Semiconductor memory devices, such as DRAM devices, require several different voltages for proper operation. One of these voltages is an internal array voltage, different than the voltage of externally supplied power, which is used by the memory cell array sensing circuitry during memory operations.
FIG. 1 shows a portion of a typical prior art semiconductor memory device 100, including a memory cell array 10, a control circuit 20, a standby internal voltage generator 30, and an active internal voltage generator 40. The two voltage generators work together to supply an internal array voltage VINTA to memory cell array 10, from an external power supply maintained at an external voltage VEXT.
Standby internal voltage generator 30 operates in both standby and active modes. A standby driving signal generator 32 within voltage generator 30 generates a first analog control signal scon to a driver 34, which drives VINTA. Standby driving signal generator 32 receives feedback on the level of VINTA, and adjusts scon as needed to keep VINTA at a reference voltage.
Active internal voltage generator 40 only operates in the active mode, in response to a signal act from control circuit 20. When act is enabled, an active driving signal generator 42, with function similar to standby driving signal generator 32, is activated. Once activated, active driving signal generator 42 generates a second analog control signal acon to a second driver 44 within voltage generator 40, which also drives VINTA. The combined driving capability of drivers 34 and 44 is therefore available to supply current during a sensing operation of the active mode.
FIG. 2 contains a timing diagram that illustrates a typical active mode operation of device 100. When an active command signal ACT is received by control circuit 20, an active control signal act is asserted. Initially, the internal array voltage VINTA may be slightly overdriven above its steady state voltage level A as active internal voltage generator 40 is activated.
Shortly after asserting act, control circuit 20 asserts a sense amplifier enable signal SEN to memory cell array 10, causing memory cell array 10 to initiate a sensing operation. The sensing operation requires numerous bit lines to be charged rapidly to the internal array voltage VINTA. The current consumed during the initial stages of the sensing operation is significant, causing the internal array voltage VINTA to dip to a voltage level B before recovering to its steady-state value A. If the voltage dip during the sensing operation is not controlled and minimized, the memory device may not work correctly.
FIG. 3 shows a portion of a second prior art semiconductor memory device 200, which attempts to overcome the voltage dip problem of memory device 100 by the addition of an overdriving circuit 50. A control circuit 20′ operates similar to control circuit 20, but also supplies an overdriving control signal Pact to the overdriving circuit 50. When overdriving circuit 50 receives Pact, it produces an overdriving signal acon′ to second driver 44.
Referring to the timing diagram shown in FIG. 4, Pact is briefly pulsed prior to the activation of sense amplifier enable signal SEN to memory cell array 10. During this pulse, overdriving circuit 50 forces driver 44 to overdrive VINTA to a voltage C when the external voltage VEXT maintains an appropriate voltage level. Voltage C is designed to be just high enough that during the high-current portion of the sensing operation the internal array voltage VINTA, which is controlled during the sensing operation in conventional fashion by standby and active driving signal generators 32 and 42, will drop back to A, and not below A as in FIG. 2. However, when the external voltage (VEXT) is set to too high of a voltage level, the internal array voltage VINTA may be overdriven to a voltage level D. In this case, the voltage level D will drop back to E after the high-current portion of the sensing operation, causing the memory device to not work correctly.